a. Field of the Invention
The present invention relates generally to a test of a memory, and more particularly to a method and an apparatus for testing memory devices mounted on a system, which is appropriate for computer terminals or small computer systems wherein users are subject to the influence of time required to boot the system.
b. Background Art
A prior art system having such memory testing function is disclosed, for example, in Japanese laid-open pat. No. 58-122700. This system has a main central processing unit (CPU) as well as another CPU or a sub-CPU. The sub-CPU is provided on a memory board to be dedicated to testing memory devices mounted on the system in order to reduce the time required for the test and to ease the load of the main CPU.
The prior art system has, however, the following disadvantages:
i) The sub-CPU is necessary for each of the memory boards, resulting in increase of the amount of hardware. PA1 ii) Memory test by the sub-CPU is limited in speed because of the sequential operations of WRITE, READ, and VERIFY instructions from outside the memory devices. PA1 iii) The memory test covers only a memory access route used by the sub-CPU, leaving untested another access route (including deta, address and control signals) which is used in normal operation by the main CPU, degrading the reliability of the system.